1. Field of Invention
The present invention relates to an integrated circuit chip and a manufacturing process of the integrated circuit chip, and more particularly to an integrated circuit chip and a manufacturing process of the integrated circuit chip capable of preventing an internal structure of the integrated circuit chip from being damaged by a crack generated by a stress.
2. Related Art
A semiconductor wafer is formed into a plurality of integrated circuit chips after the semiconductor manufacturing processes are performed. Each integrated circuit chip includes a device region and a peripheral circuit region. The finished semiconductor wafer has to be sliced into bare chips, which are then packaged and tested to form the integrated circuit chips.
In the process of slicing the wafer, the generated slicing stress tends to cause a crack, which may damage the internal circuit of the integrated circuit chip. Thus, a sealing ring structure is formed between the integrated circuit chip and a scribing line in order to protect the structure of the integrated circuit chip.
Referring to FIGS. 1a and 1b, a conventional integrated circuit chip 1 includes a substrate 11, a device stack layer 12 and a sealing ring stack layer 13. The substrate 11 has a sealing region 111 and a chip region 112. The sealing region 111 is disposed around the chip region 112. The device stack layer 12 is disposed within the chip region 112 of the substrate 11 and has internal traces (not shown). The sealing ring stack layer 13 is disposed within the sealing region 111 of the substrate 11 and has a sealing base layer 131 and a plurality of sealing layers 132. The sealing base layer 131 is an electrically conductive region, which provides a ground for the sealing ring stack layer 13 and is formed by a boron-doped silicon or a phosphorus-doped silicon. Each sealing layer 132 is an electrically conductive layer made of aluminum, silver, copper or their alloy.
As shown in FIG. 2, the flip chip packaging technology is generally adopted with the progress of the technology of packaging. An active surface 14 of the integrated circuit chip 1 is directly electrically connected with a carrier 2. During the packaging process, the sealing base layer 131 cannot isolate a crack 15 generated by an external force from entering the integrated circuit chip 1 because a gap exists between the bottom surface of the substrate 11 and the sealing ring stack layer 13. Thus, the internal traces in the device stack layer 12 tend to be damaged. The crack 15 may not damage the internal traces during the packaging process. However, when the tests including a temperature cycle test and a thermal shock test are performed after the chip is packaged, the crack 15 may further enter the integrated circuit chip 1 due to thermal expansion and contraction, thereby damaging the internal traces of the integrated circuit chip 1. In addition, the integrated circuit chip 1 tends to be damaged by the external force in a transporting process or other manufacturing processes.
It is therefore an important subject of the present invention to provide an integrated circuit chip and a manufacturing process of the integrated circuit chip to prevent an internal structure of the integrated circuit chip from being damaged by a crack generated by a stress.